1. Field of the Invention
This invention relates generally to a method of manufacturing high density, high performance semiconductor devices that have structures with dimensions less than conventionally available from current semiconductor manufacturing technology. More specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices with structures that have selectable dimensions less than dimensions conventionally available from current semiconductor manufacturing technology. Even more specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices with structures that have selectable dimensions less than dimensions conventionally available from current photolithography technology.
2. Discussion of the Related Art
The industry demand for reduced price products containing semiconductor devices is increasing at an ever-increasing rate. The increased demand for improved high performance products is being met by improving performance at the functional level of the semiconductor device circuitry. As these products become commodities, and in view of the increasing price erosion for these products, it is becoming increasingly necessary to manufacture these products at reduced cost. One example of cost reduction is to decrease the manufacturing cycle time thereby increasing factory capacity. Another example of cost reduction is to reduce the total number of process steps to manufacture the product. A further example of cost reduction is to increase the density by packing more transistors into a given area of silicon. This makes more die per wafer available for sale to further amortize the cost of the product.
Typically, an increase in density is dependent on feature size reduction such as shrinking the minimum dimensions from 500 nm to 350 nm to 250 nm with smaller decrements in between each step down. As price erosion continues, more density, that is, more die per wafer, is required to maintain the average selling price for a fixed area of silicon. Unfortunately, requirements to shrink the feature size have surpassed the current available semiconductor manufacturing technology with the major bottleneck being the minimum feature size available from current photolithography technology. Although the following discussion is about polysilicon gate structures it should be appreciated that the discussion is also applicable to other structures.
The photoresist mask that defines the gate structures dictates the future polysilicon shape and width of the gate with one of its metrics being a critical dimension (CD). It is important to have a near vertical photoresist profile for the gate mask since some of the photoresist will be consumed during the etch process, which requires that the critical dimension at the top of the photoresist is the same as at the bottom. This etch induced consumption will change the feature size and shape of the photoresist mask. The underlying polysilicon gate will be replicated from the shape of the photoresist mask. Therefore, an imperfect gate mask will result in undesirable polysilicon gates and poor critical dimension control.
In leading state-of-the-art process technologies, there have been attempts to reduce the final dimension or critical dimension beyond the minimum dimension. Some of these attempts include a process of over-exposing the photoresist. Another method is to trim the printed feature size utilizing an etch process. However, these methods only reduce the main feature size while the overall space between adjacent features increases.
Because the pitch of the device (the length of one feature and one space) does not decrease, there is no gain in density. The ultimate limiting factors are the parameters of the manufacturing process that limit the minimum achievable pitch. Some of the limiting factors are the parameters of the lithographic system being used to manufacture the semiconductor device. For example, one limiting factor is the wavelength of the radiation utilized to transfer the pattern on the reticle to the photoresist on the wafer being manufactured.
Another limiting factor of a photolithographic system is the quality of the lens systems that reduces the image on the reticle to that which is imaged onto the wafer, typically a 5.times.reduction. In order to improve the photolithographic system, various steps have been pursued one of which is to reduce the wavelength of the illuminating radiation. Currently, ultraviolet (UV) is used, however the lens materials available that will efficiently transmit ultraviolet radiation are limited and those that are available are expensive.
Other radiation sources such as x-ray or electron-beam lithography systems have been proposed as well. These alternative sources have the potential to further decrease the feature size of the resulting semiconductor device. However, the systems utilizing x-ray or electron-beam source are extremely expensive and require extensive shielding.
Another alternative to the current technology utilizes a deep ultraviolet (DUV) for quarter micron process technology, using a source radiation having a wavelength of 248 nm. To insure the printed minimum features have an acceptable depth of focus and photoresist profile, the printed features are usually targeted to be slightly larger than the illuminating wavelength. In some cases, optical proximity correction (OPC) and phase shift (PS) are also used to enhance the image when printing is at or below the wavelength of illuminating radiation. However, these methods are very expensive and the density increase is only a comparatively small gain and as such does not justify the cost that is associated with these exotic methods.
Therefore, what is needed is a method of manufacturing a semiconductor device, utilizing the currently available photolithographic systems that can provide a feature size substantially smaller without the use of the more expensive lithographic systems.